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[Graph Drawing] dds(heli)

Description: DDS用verilog 实现，可以实现方波、正弦和三角-DDS using verilog realized, can be square wave, sinusoidal and triangular
Platform: | Size: 428032 | Author: qian | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Platform: | Size: 190464 | Author: 赵一 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ-Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wave, step adjustable. Frequency range 1HZ- 10MHZ
Platform: | Size: 117760 | Author: tiancheng | Hits:

[VHDL-FPGA-Verilog] dds

Description: 用VERILOG语言实现的dds(直接数字频率合成器)-VERILOG language with the dds (DDS)
Platform: | Size: 104448 | Author: 叶少朋 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: FPGA控制AD9854的源文件，verilog，附有简单文档。-FPGA to control the AD9854 source file, verilog, with a simple document.
Platform: | Size: 820224 | Author: 柴佳 | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds 驱动 ad9851 fpga vhdl-ad9851 dds ad9851 fpga vhdl
Platform: | Size: 1544192 | Author: ZHANGLONG | Hits:

[VHDL-FPGA-Verilog] DDS_FINAL

Description: My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different frequency. We can change the frequency using frequency selector input. Please accept this project. We use the SPARTAN 3E 500 device to implement it.
Platform: | Size: 437248 | Author: Raju Kumar | Hits:

[VHDL-FPGA-Verilog] DDSVerilog

Description: DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation
Platform: | Size: 71680 | Author: caixiang | Hits:

[VHDL-FPGA-Verilog] dds

Description: 这是用VERILOG描写的一个DDS的实例，涉及到一些lpm的运用希望对大家有用-it‘s useful。
Platform: | Size: 881664 | Author: tom | Hits:

[VHDL-FPGA-Verilog] MyDDS

Description: 利用查找表法编写的DDS的verilog程序，节省了利用IP核实现需要的资源，软件为ISE，-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
Platform: | Size: 2891776 | Author: 蜡笔 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 这个是我自己用VHDL语言写的两相数字信号发生器程序 D/A用的是DAC904-This is for my own use VHDL, written procedures for two-phase digital signal generator D/A using a DAC904
Platform: | Size: 1370112 | Author: 马骋 | Hits:

[SCM] AD9910

Description: 这是AD9910 DDS芯片的verilog配置程序，经调试已成功，可以供大家参考。-AD9910 verilog configuation.
Platform: | Size: 1024 | Author: da niu | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 在FPGA中实现频率源的设计,使用硬件描述语言加以实现。-design DDS with verilog language
Platform: | Size: 125952 | Author: lin | Hits:

[VHDL-FPGA-Verilog] dds

Description: 用Verilog语言实现基于dds技术的余弦信号发生器，其输出位宽为16比特-Dds with the Verilog language technology based on the cosine signal generator, the output bit width is 16 bits
Platform: | Size: 8192 | Author: xiaobai | Hits:

[VHDL-FPGA-Verilog] DDS__FPGA

Description: 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容
Platform: | Size: 92160 | Author: 小何 | Hits:

[Other Embeded program] DDS

Description: Verilog语言实现基于DDS技术的余弦信号发生器，输出位宽16Bit-Verilog language technology based on the cosine DDS signal generator, the output bit width 16Bit
Platform: | Size: 4096 | Author: 柏承建 | Hits:

[VHDL-FPGA-Verilog] ddsfinal1

Description: verilog语言实现的dds代码，并行通信，生成四种波形，大赛编写的代码，modelsim仿真-verilog language dds code,modelsim debug
Platform: | Size: 1137664 | Author: 杨天 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 关于用FPGA制作的DDS源代码。用的是verilog语言，用的是xlinx的软件-Produced with the DDS on FPGA source code. Using verilog language, using xlinx software
Platform: | Size: 5120 | Author: 张君 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 采用verlog编写的tlc5615驱动程序，并利用了rom核实现了dds功能-Using verlog written tlc5615 driver, and use the rom-core functions to achieve a dds
Platform: | Size: 619520 | Author: ranshaoqiang | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 能在DDS中用Verilog HDL语言实现FM,AM,FSK,ASK,PSK，结合可编程器件FGPA等等就能实现这些功能 -DDS can be used in Verilog HDL language FM, AM, FSK, ASK, PSK, etc. FGPA programmable devices can be combined to achieve these functions
Platform: | Size: 6281216 | Author: 王凡 | Hits:
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